LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.numeric_std.all; 

ENTITY inst_mem IS
	PORT ( Address		: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		   Instruction	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		   Immediate	: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END inst_mem;

ARCHITECTURE Behavior OF inst_mem IS
	
	SIGNAL memory		: STD_LOGIC_VECTOR(0 TO 47);
	
BEGIN
				memory(0 TO 7)   <= "10110001"; --add r1,imed
				memory(8 TO 15)  <= "00101011";
				memory(16 TO 23) <= "10001110";
				memory(24 TO 31) <= "11001100";
				memory(32 TO 39) <= "01110100";
				memory(40 TO 47) <= "01010101";
				Instruction(7) <= memory(to_integer(unsigned(Address)));
				Instruction(6) <= memory(to_integer(unsigned(Address)) + 1);
				Instruction(5) <= memory(to_integer(unsigned(Address)) + 2);
				Instruction(4) <= memory(to_integer(unsigned(Address)) + 3);
				Instruction(3) <= memory(to_integer(unsigned(Address)) + 4);
				Instruction(2) <= memory(to_integer(unsigned(Address)) + 5);
				Instruction(1) <= memory(to_integer(unsigned(Address)) + 6);
				Instruction(0) <= memory(to_integer(unsigned(Address)) + 7);
				Immediate(7) <= memory(to_integer(unsigned(Address)) + 8);
				Immediate(6) <= memory(to_integer(unsigned(Address)) + 9);
				Immediate(5) <= memory(to_integer(unsigned(Address)) + 10);
				Immediate(4) <= memory(to_integer(unsigned(Address)) + 11);
				Immediate(3) <= memory(to_integer(unsigned(Address)) + 12);
				Immediate(2) <= memory(to_integer(unsigned(Address)) + 13);
				Immediate(1) <= memory(to_integer(unsigned(Address)) + 14);
				Immediate(0) <= memory(to_integer(unsigned(Address)) + 15);
END Behavior;